module clka_to_clkb(
    input clka,
    input clkb,
    input clka_in,
    output clkb_out
);
assign clkb_out = signal1;
reg signal0;
reg signal1;
always @(posedge clka ) begin
    if(signal0^signal1) begin
        signal0 <= signal0;
    end
    else begin
        signal0 <= clka_in;
    end
end
always @(posedge clkb ) begin
    signal1 <= signal0;
end
endmodule